Pipelined RISC-v CPU HDL Implementation

The classic five stage in-order pipelined RISC design implemented in Chisel for a university assignment. Find the project over on github.

Features:

  • Full support for RISC-V 32-bit
  • Pipelined design
  • Proper hazard detection and avoidance
  • Bimodal branch predictor and a BTB
Last updated: Jun 22, 2025